The present invention generally concerns circuits for controlling power field-effect transistors (FETs), and particularly a power stage of quasi-complementary symmetry, i.e. a stage which includes a first transistor in common-source configuration and a second transistor in common-drain configuration, for driving loads of mixed type.
Half-bridge power stages are commonly used for driving brushless motors, stepper motors, and for transmitting logic signals at high-voltage. When the fabrication technology permits, it is preferable to utilize field effect transistors for the output, for example, VDMOS (Vertical Double Diffused MOS transistors) or LDMOS (Lateral Double Diffused MOS transistors), since these provide significant advantages over bipolar transistors of comparable current-carrying capacity. In a typical half-bridge stage, the two transistors of the stage are connected in series between the two power supply nodes, and are driven alternatively into conduction by appropriate control circuits which are coupled to their gate terminals.
While it is possible to use a complementary pair of output transistors (i.e. PMOS and NMOS), this solution is seldom used because a greater area is required for a PMOS transistor. (As is well known, for a PMOS transistor the ratio between the internal on-resistance Ron and the area required is more than double the ratio for a comparable NMOS transistor). The necessity to minimize the area conversely favors the use of a pair of output transistors which are both N-channel, to realize a power stage which is of quasi-complementary symmetry including a first transistor (or stage) in common-source configuration, at an output node of which a second transistor (stage) in common-drain configuration is connected.
As is well known, a common-drain stage (or transistor) requires a gate drive potential (Vb) which is higher than the common potential of the drain (VDD), in order to assure a suitable turn-on. Such an elevated drive voltage Vb is commonly generated within the integrated circuit, by means of a voltage-multiplying circuit.
Moreover, the load driven by a half-bridge power stage will almost always be a reactive load, and often will have "mixed" characteristics. For example, in the case of electric motors, the load acts like a capacitive load at start-up, but while the velocity is being regulated (i.e. in phases where reactive current is being recirculated), the load behaves like an inductor.
In the presence of capacitive loads (voltage inertial loads), it is necessary to protect the pull-up transistor from the inevitable voltage spikes which may cause the gate/source breakdown voltage to be exceeded (particularly in view of the overdriven gate of the common-drain-configured transistor). This protection function is commonly handled by at least one pair of back-to-back zener diodes, connected between the gate and source of the transistor which is overdriven by the high voltage Vb on its gate.
This problem does not exist for the other power transistor, since the source of this other transistor is always held at a common potential (ground potential usually).
The two FIGS. 1A and 1B show a typical circuit configuration for a half-bridge power stage, which includes a pair of FETs M1 and M2. The upper transistor (M2) is overdriven by a gate voltage Vb which is higher than its drain voltage VDD. The drive of the transistor M2 is commanded by a pair of signals SWD and SWS, which are respectively connected to charge and to discharge the gate node of the transistor M2, by means of respective current generators Is and Id.
FIG. 1A shows the case of a capacitive load. In this operating regime, the zener diodes D1 and D2 limit the gate-source voltage VGS of the transistor M2, when it is turned on in the presence of voltage inertial loads (capacitive load CL). When the zener protection diodes D1 and D2 are turned on, they can carry current Is, with forward and reverse bias respectively.
In an inductive load condition, as shown in FIG. 1B, the zener protection diodes D1 and D2 limit (in the opposite direction) the maximum gate-source voltage VGS of the transistor M2 (which in the illustrated phase is off), while the transistor M1 makes the transition from on-state to off-state. These conditions may be seen, for example, during the speed-regulation of an electric motor. Under such conditions, due to the effect of the current Io which flows through the inductive load (discharge current of the energy stored in the inductance LI), and across the recirculation diode D3 intrinsic to the integrated structure of the FET M2, the output voltage Vo rises to a value given by: EQU Vo=VDD+V.sub.D3,
which is a value higher than the supply voltage VDD. The zener diodes D1 and D2 are therefore turned on and carry current Id, in forward and reverse bias current directions respectively.
Under these conditions, a current Ilo equal to Id is absorbed at the output node Vo. This current absorption across the output node of the power stage begins when the output voltage Vo exceeds a threshold value given by: EQU Vo.sub.t =V.sub.D2 +Vz,
where V.sub.D2 is the drop across forward biased zener D2 and Vz is the zener voltage of the diode D1. Therefore the threshold value Vo.sub.t is necessarily less than the maximum value of the output voltage Vo.
This current Ilo (due to the presence of the zener diodes for protection of the common-drain-configured transistor), is absorbed under conditions of high output impedance, and introduces some imprecision in the current which flows through the load. Indeed, during the phases of recirculation (with M2 off), and when the voltage of the output node exceeds the threshold voltage (Vo&gt;V.sub.D2 +Vz), the circuit absorbs a current Id from the load through the protection diodes D1 and D2.
This current absorption changes the time constant for discharge of the inductance, and introduces therefore an imprecision which may be intolerable in many applications.
Another drawback is represented by the fact that, during testing of the integrated circuits, the presence of the current absorbed at the output node may obstruct verification of the high-voltage integrity of the common-source connected transistor (M1). Indeed, the absorption of current across the protective diodes D1 and D2 prevents determination of absorption due to possible leakage current into the substrate of the transistor M1.
It is therefore a primary object of the present invention to provide a power stage of quasi-complementary symmetry, including a common-source FET and a common-drain FET, with a reduced absorption of current under the conditions of high impedance of the output.
This objective is effectively obtained by substantially decoupling the driving node of the upper (common-drain) transistor from the output node of the stage. This prevents the current generator Id, which discharges the control node, from absorbing current from the load connected to the output stage, during a phase of high output impedance, and when the inertial swing of voltage on the output node exceeds the threshold value which causes turn on of the zener protection diodes connected between the output node of the stage and the control node of the upper (common-drain) transistor.
An effective decoupling may be realized by using a bipolar transistor which has its base connected to the output node of the stage, and is connected to provide the current drawn from the discharge generator of the driving node of the upper common-drain transistor, absorbing it from the high-voltage overdriven supply node. In practice, the current absorbed from the load turns out to be a fraction of the current from the discharge current generator, in a relation given by the current gain of the decoupling transistor. Therefore, the decoupling transistor may be realized by a transistor of high gain, or alternatively by a Darlington stage.
To absorb the current drawn by the discharge generator from the node at overdriven voltage might be considered as a drawback in some applications, because this overdriven voltage is usually provided by a charge pump or voltage multiplier, which has a limited current capacity. To this end, it may also be considered that during the absorption, the overdriven transistor is off, and hence momentarily does not require overdriving from the high voltage.
According to an alternative embodiment of the invention, even this possible disadvantageous aspect is superseded by providing circuitry for absorbing the necessary current from the supply node VDD instead of absorbing it from the voltage overdriven node Vb. This alternative solution is particularly useful when the overdriven node Vb drives multiple output stages.
According to this alternative embodiment of the invention, the decoupling is obtained by using a field effect transistor instead of a bipolar transistor. This permits absorption of the current directly from the supply line VDD in order to not overload the overdriven node Vb. By providing a FET instead of a bipolar transistor, the problem of saturation of the bipolar transistor, when connected to the supply line VDD, is avoided. Moreover, when a condition of saturation is seen, the drastic reduction of the bipolar transistor current gain (causing a losing of the capacity to effectively decouple the output node of the stage) is also avoided. Naturally, this problem, related to saturation, is not present when a FET transistor is used for decoupling, since saturation for a FET follows a purely resistive type of behavior of the transistor.